SH7764 Datasheet, PDF (430/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 12 Direct Memory Access Controller (DMAC)
Bit
17
16
15, 14
Initial
Bit Name Value
AM
0
AL
0
DM[1:0] 00
R/W
R/W
R/W
R/W
Descriptions
Acknowledge Mode
Selects whether DACK is output in data read cycle or in
data write cycle.
This bit is valid only in CHCR0 and CHCR1.
0: DACK output in read cycle
1: DACK output in write cycle
Acknowledge Level
Specifies whether the DACK and DTEND signal output
is high active or low active.
This bit is valid only in CHCR0 and CHCR1.
0: Low-active output of DACK and DTEND
1: High-active output of DACK and DTEND
Destination Address Mode
Specify whether the DMA destination address is
incremented, decremented, or left fixed.
00: Fixed destination address
01: Destination address is incremented
+1 in byte units transfer
+2 in word units transfer
+4 in longword units transfer
+16 in 16-byte units transfer
+32 in 32-byte units transfer
10: Destination address is decremented
–1 in byte units transfer
–2 in word units transfer
–4 in longword units transfer
Setting prohibited in 16/32-byte units transfer
11: Setting prohibited
Rev. 1.00 Nov. 22, 2007 Page 374 of 1692
REJ09B0360-0100