SH7764 Datasheet, PDF (774/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 19 Ethernet Controller (EtherC)
19.3.10 Delayed Collision Detect Counter Register (CDCR)
CDCR is a 32-bit counter that indicates the number of all delayed collisions that occurred on the
line after the start of data transmission. When the value in this register reaches H'FFFFFFFF,
count-up is halted. The counter value is cleared to 0 by a write to this register with any value.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COSDC[31:16]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
COSDC[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
31 to 0
Bit Name
Initial
Value R/W Description
COSDC[31:0] All 0 R/W Delayed Collision Detect Count
These bits indicate the number of all delayed collisions
after the start of data transmission.
Rev. 1.00 Nov. 22, 2007 Page 718 of 1692
REJ09B0360-0100