SH7764 Datasheet, PDF (459/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 12 Direct Memory Access Controller (DMAC)
CLKOUT
Bus cycle
DREQ
(Rising edge)
CPU
Burst acceptance
DMAC
DMAC
DACK
(High-active)
: Non-sensitive period
Figure 12.15 Example of DREQ Input Detection in Burst Mode Edge Detection
CLKOUT
Bus cycle
DREQ
(Overrun 0,
High-level)
DACK
(High-active)
CLKOUT
Bus cycle
DREQ
(Overrun 1,
High-level)
CPU
1st acceptance
DMAC
2nd acceptance
CPU
1st acceptance
Acceptance
started
DMAC
2nd acceptance
DMAC
3rd acceptance
DACK
(High-active)
: Non-sensitive period
Acceptance
started
Acceptance
started
Figure 12.16 Example of DREQ Input Detection in Burst Mode Level Detection
Rev. 1.00 Nov. 22, 2007 Page 403 of 1692
REJ09B0360-0100