SH7764 Datasheet, PDF (1037/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 21 USB 2.0 Host/Function Module (USB)
(2) Control Transfers when the Function Controller Function is Selected
(a) Setup Stage
This module always sends an ACK response in response to a setup packet that is normal with
respect to this module. The operation of this module operates in the setup stage is noted below.
(i) When a new USB request is received, this module sets the following registers:
• Set the VALID bit in INTSTS0 to 1.
• Set the PID bit in DCPCTR to NAK.
• Set the CCPL bit in DCPCTR to 0.
(ii) When a data packet is received right after the SETUP packet, the USB request parameters are
stored in USBREQ, USBVAL, USBINDX, and USBLENG.
Response processing with respect to the control transfer should always be carried out after first
setting VALID = 0. In the VALID = 1 state, PID = BUF cannot be set, and the data stage cannot
be terminated.
Using the function of the VALID bit, this module is able to interrupt the processing of a request
currently being processed if a new USB request is received during a control transfer, and can send
a response in response to the newest request.
Also, this module automatically judges the direction bit (bit 8 of the bmRequestType) and the
request data length (wLength) of the USB request that was received, and then distinguishes
between control read transfers, control write transfers, and no-data control transfers, and controls
the stage transition. For a wrong sequence, the sequence error of the control transfer stage
transition interrupt is generated, and the software is notified. For information on the stage control
of this module, see figure 21.7.
(b) Data Stage
Data transfers corresponding to USB requests that have been received should be done using the
DCP. Before accessing the DCP buffer memory, the access direction should be specified using the
ISEL bit in CFIFOSEL.
If the data being transferred is larger than the size of the DCP buffer memory, the data transfer
should be carried out using the BRDY interrupt for control write transfers and the BEMP interrupt
for control read transfers.
With control write transfers during high-speed operation, the NYET handshake response is carried
out based on the state of the buffer memory.
Rev. 1.00 Nov. 22, 2007 Page 981 of 1692
REJ09B0360-0100