SH7764 Datasheet, PDF (1314/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 24 Video Display Controller (VDC2)
24.6.15 Sync Signal Control Register (SYNCNT)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RGB_
EX_V EX_H
VSYNC HSYNC DEV DEH DEC COM


 _TIM 
 _{_TIM _TIM} 
 _{_TIM _TIM _TIM _TIM _TIM _TIM}
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R/W R R R/W R/W R R R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
EX_V_ EX_H_





 _{TYPE TYPE} 
Initial value: 0
0
0
0
0
0
0
0
0
R/W: R R R R R R R/W R/W R
6
5
4
3
2
1
0
VSYNC HSYNC DEV DEH DEC COM
 _{_TYPE _TYPE _TYPE _TYPE _TYPE _TYPE}
0
0
0
0
0
0
0
R R/W R/W R/W R/W R/W R/W
Bit
Bit Name
31 to 29 
Initial
Value
All 0
28
RGB_TIM 0
27, 26 
All 0
25
EX_V_TIM 0
24
EX_H_TIM 0
23 to 22 
All 0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Specifies the RGB data output timing.
0: Outputs data at the rising edge of the panel
clock
1: Outputs data at the falling edge of the panel
clock
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Specifies the external VSYNC input timing.
0: Latches the external VSYNC at the rising edge
of the panel clock
1: Latches the external VSYNC at the falling edge
of the panel clock
R/W Specifies the external HSYNC input timing.
0: Latches the external HSYNC at the rising edge
of the panel clock
1: Latches the external HSYNC at the falling edge
of the panel clock
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 1.00 Nov. 22, 2007 Page 1258 of 1692
REJ09B0360-0100