SH7764 Datasheet, PDF (396/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Memory Controller Unit (MCU)
11.9 Bus Arbitration
This module has two arbitration functions: one is arbitration of the accesses between the various
internal modules, and the other is arbitration of the bus requests from the external devices.
11.9.1 Arbitration of Accesses between Internal Modules
This module arbitrates SDRAM or SRAM accesses between the CPU, various pixel bus modules,
and LCDC. (SRAM cannot be accessed by the pixel bus modules or LCDC.) Since SDRAM
accesses are often used for the applications requiring real-time operation such as reading out the
image data for display, it is significant to assign the appropriate priority to the modules so that the
requirements of the modules such as response time and bandwidth are satisfied. The policy of
priority assignment is given below.
1. The highest priority (level 0) is given to SDRAM control such as refreshing and page
management.
Memory is refreshed according to the memory refresh interval specified separately.
2. A high priority (level 1) is given to the display controller (VDC2) and LCD controller (LCDC)
to support transfer of the output data for display, which requires real-time operation.
3. A lower priority (level 2 or 3) is given to the other accesses.
Either level can be selected for each module.
Figure 11.20 shows the arbitration of the access requests. In the figure, priority level 1 is given to
the VDC2 and LCDC, and the round-robin method is used to arbitrate the accesses between them.
Similarly, priority level 3 is given to the SuperHyway modules (CPU, DMAC, EtherC, and
others), ATAPI, and G2D command/data; and the round-robin method is used to arbitrate the
accesses between them. Access requests are arbitrated using the request signals that are being
asserted at the arbitration timing. Figure 11.21 shows an arbitration example in which the priority
levels of SuperHyway modules and G2D module are raised to level 2. Arbitration is carried out
only between the modules indicated by the solid lines.
The request-masking function is provided to limit memory accesses during NMI interrupt
processing. This function allows assigning relatively higher percentage of memory use by the CPU
interrupt processing upon NMI interrupt generation. Requests from different modules can be
masked separately through the request mask setting register (RQM) so that the optimum settings
can be made according to the usage of NMI.
For the LCDC, any of priority levels 1, 2, and 3 can be selected through register setting.
Rev. 1.00 Nov. 22, 2007 Page 340 of 1692
REJ09B0360-0100