SH7764 Datasheet, PDF (1362/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 25 NAND Flash Memory Controller (FLCTL)
Initial
Bit
Bit Name Value R/W Description
1
TREND 0
R/W Processing End Flag Bit
Indicates that the processing performed in the specified
access mode has been completed. The write value
should always be 0.
0
TRSTRT 0
R/W Transfer Start
By setting this bit from 0 to 1 when the TREND bit is 0,
processing in the access mode specified by the access
mode specification bits ACM[1:0] is initiated.
0: Stops transfer
1: Starts transfer
25.4 Operation
25.4.1 Operating Modes
Two operating modes are supported.
• Command access mode
• Sector access mode
The ECC generation and error check are performed in sector access mode.
25.4.2 Register Setting Procedure
Figure 25.2 shows the register setting flow required for accessing to the flash memory.
Rev. 1.00 Nov. 22, 2007 Page 1306 of 1692
REJ09B0360-0100