SH7764 Datasheet, PDF (809/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 20 Ethernet Controller Direct Memory Access Controller (E-DMAC)
20.2.1 E-DMAC Mode Register (EDMR)
EDMR is a 32-bit readable/writable register that specifies E-DMAC operating mode. This register
should usually be set at initialization after a reset. If the EtherC and E-DMAC are initialized with
this register during data transmission, abnormal data may be transmitted on the line. It is
prohibited to modify the operating mode while transmission or reception function is enabled.
Before modifying the operating mode, the EtherC and E-DMAC should be initialized by setting
the software reset bit (SWR). Note that it takes 64 cycles of internal bus clock Bφ for the EtherC
and E-DMAC to be completely initialized. Therefore, the registers in the EtherC or E-DMAC
should be accessed after that.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
— DE
DL[1:0]
—
—
— SWR
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R/W R/W R/W R R R R/W
Bit
31 to 7
Bit Name

6
DE
5, 4
DL[1:0]
Initial
Value
All 0
0
00
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Big/Little Endian Mode
0: Big endian (longword access)
1: Little endian (longword access)
The setting applies to transmit and receive data.
The setting does not apply to transmit/receive
descriptors or registers (only big endian mode is
available).
R/W Transmit/Receive Descriptor Length
00: 16 bytes (Initial value)
01: 32 bytes
10: 64 bytes
11: 16 bytes
Rev. 1.00 Nov. 22, 2007 Page 753 of 1692
REJ09B0360-0100