SH7764 Datasheet, PDF (1471/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 28 Power-Down Mode
28.3.2 Module Stop Register 0 (MSTPCR0)
MSTPCR0 is a 32-bit readable/writable register that can individually start or stop the module
assigned to each bit.
MSTPCR0 can be accessed only in longwords.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
— — — — — — — — — INTC DMAC — H-UDI — UBC —
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R/W R/W R R/W R R/W R
Bit: 15 14
LCDC —
Initial value: 0
0
R/W: R/W R
13 12 11 10 9
8
7
6
5
4
TMU FLCTL — SCIF2 SCIF1 SCIF0ETHER IIC ATAPI G2D
0
0
0
0
0
0
0
0
0
0
R/W R/W R R/W R/W R/W R/W R/W R/W R/W
3
2
1
— VDC2 —
0
0
0
R R/W R
0
USB
0
R/W
Bit
31 to 23
Bit Name

Initial
Value
All 0
22
INTC
0
21
DMAC
0
20

0
R/W
R
R/W
R/W
R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
INTC Module Stop Bit
When set to 1, the clock supply to the INTC module is
halted.
0: INTC operates
1: Clock supply to INTC is halted
DMAC Module Stop Bit
When set to 1, the clock supply to the DMAC module is
halted.
0: DMAC operates
1: Clock supply to DMAC is halted
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Nov. 22, 2007 Page 1415 of 1692
REJ09B0360-0100