SH7764 Datasheet, PDF (115/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 3 Instruction Set
Item
Format
Description
Privileged mode
"Privileged" means the instruction can only be executed
in privileged mode.
T bit
Value of T bit after —: No change
instruction execution
New

"New" means the instruction which has been newly
added in the SH-4A with H’20-valued VER bits in the
processor version register (PVR).
Note: Scaling (×1, ×2, ×4, or ×8) is executed according to the size of the instruction operand.
Table 3.4 Fixed-Point Transfer Instructions
Instruction
Operation
Instruction Code
Privileged T Bit New
MOV #imm,Rn
imm → sign extension → Rn 1110nnnniiiiiiii —
——
MOV.W @(disp*,PC), Rn (disp × 2 + PC + 4) → sign
extension → Rn
1001nnnndddddddd —
——
MOV.L @(disp*,PC), Rn (disp × 4 + PC & H'FFFF FFFC 1101nnnndddddddd —
+ 4) → Rn
——
MOV Rm,Rn
Rm → Rn
0110nnnnmmmm0011 —
——
MOV.B Rm,@Rn
Rm → (Rn)
0010nnnnmmmm0000 —
——
MOV.W Rm,@Rn
Rm → (Rn)
0010nnnnmmmm0001 —
——
MOV.L Rm,@Rn
Rm → (Rn)
0010nnnnmmmm0010 —
——
MOV.B @Rm,Rn
(Rm) → sign extension → Rn 0110nnnnmmmm0000 —
——
MOV.W @Rm,Rn
(Rm) → sign extension → Rn 0110nnnnmmmm0001 —
——
MOV.L @Rm,Rn
(Rm) → Rn
0110nnnnmmmm0010 —
——
MOV.B Rm,@-Rn
Rn-1 → Rn, Rm → (Rn)
0010nnnnmmmm0100 —
——
MOV.W Rm,@-Rn
Rn-2 → Rn, Rm → (Rn)
0010nnnnmmmm0101 —
——
MOV.L Rm,@-Rn
Rn-4 → Rn, Rm → (Rn)
0010nnnnmmmm0110 —
——
MOV.B @Rm+,Rn
(Rm)→ sign extension → Rn, 0110nnnnmmmm0100 —
Rm + 1 → Rm
——
MOV.W @Rm+,Rn
(Rm) → sign extension → Rn, 0110nnnnmmmm0101 —
Rm + 2 → Rm
——
MOV.L @Rm+,Rn
(Rm) → Rn, Rm + 4 → Rm 0110nnnnmmmm0110 —
——
MOV.B R0,@(disp*,Rn) R0 → (disp + Rn)
10000000nnnndddd —
——
MOV.W R0,@(disp*,Rn) R0 → (disp × 2 + Rn)
10000001nnnndddd —
——
MOV.L Rm,@(disp*,Rn) Rm → (disp × 4 + Rn)
0001nnnnmmmmdddd —
——
Rev. 1.00 Nov. 22, 2007 Page 59 of 1692
REJ09B0360-0100