SH7764 Datasheet, PDF (331/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Initial
Bit
Bit Name Value R/W
12 to 10 SRAS2 to 111 R/W
SRAS0
9, 8
SRP1 and 11
R/W
SRP0
7 to 5 SRC2 to 111 R/W
SRC0
Section 11 Memory Controller Unit (MCU)
Description
These bits specify the minimum number of cycles
(Tras) from ACT command issuance to PRE command
issuance in the same bank.
000: 7 cycles
001: 8 cycles
010: 9 cycles
011: 10 cycles
100: 11 cycles
101: 12 cycles
110: 13 cycles
111: 14 cycles
These bits specify the number of cycles (Trp) from PRE
command issuance to ACT command issuance.
00: 2 cycles
01: 3 cycles
10: 4 cycles
11: 5 cycles
These bits specify the number of cycles (Trc) in the
same bank for the following times.
(1) From ACT command issuance to auto refresh
(2) From ACT command issuance to ACT command
issuance
000: 8 cycles
001: 9 cycles
010: 10 cycles
011: 11 cycles
100: 12 cycles
101: 13 cycles
110: 14 cycles
111: 15 cycles
Rev. 1.00 Nov. 22, 2007 Page 275 of 1692
REJ09B0360-0100