SH7764 Datasheet, PDF (360/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Memory Controller Unit (MCU)
Initial
Bit
Bit Name Value R/W
19

0
R
18 to 16 IWRRD2 to 111 R/W
IWRRD0
15

0
R
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
Idle Cycles between Read and Read Access Cycles to
Different Area
These bits specify the number of idle cycles to be
inserted after a read access to the memory connected
to area 3.
The idle cycles specified in these bits are inserted
between a read access cycle to area 3 and a read
access cycle to area 0.
000: No idle cycles inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 3 idle cycles inserted
100: 4 idle cycles inserted
101: 5 idle cycles inserted
110: 6 idle cycles inserted
111: 7 idle cycles inserted
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 1.00 Nov. 22, 2007 Page 304 of 1692
REJ09B0360-0100