SH7764 Datasheet, PDF (427/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 12 Direct Memory Access Controller (DMAC)
Initial
Bit
Bit Name Value R/W Descriptions
27 to 25 RPT[2:0] 000
R/W DMA Setting Renewal Specify
These bits are enabled in CHCR0 to CHCR3.
000: Normal mode
001: Repeat mode
SAR/DAR/TCR used as repeat area
010: Repeat mode
DAR/TCR used as repeat area
011: Repeat mode
SAR/TCR used as repeat mode
100: Reserved (setting prohibited)
101: Reload mode
SAR/DAR/TCR used as reload area
110: Reload mode
DAR/TCR used as reload area
111: Reload mode
SAR/TCR used as reload area
24
—
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
23
DO
0
R/W DMA Overrun
Selects whether DREQ is detected by overrun 0 or by
overrun 1. This bit is valid only in CHCR0 and CHCR1.
0: Detects DREQ by overrun 0
1: Detects DREQ by overrun 1
22
—
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
21
DVMD
0
R/W Division Transfer Mode Specification
Specifies the execution of the DMA transfer in 16-byte
units between the FLCTL and external memory.
When the FLCTL is not used, this bit should always be
cleared to 0.
Rev. 1.00 Nov. 22, 2007 Page 371 of 1692
REJ09B0360-0100