SH7764 Datasheet, PDF (820/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 20 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Initial
Bit
Bit Name Value R/W Description
26
TABTIP
0
R/W Transmit Abort Detect Interrupt Enable
0: Transmit abort detect interrupt is disabled
1: Transmit abort detect interrupt is enabled
25
RABTIP
0
R/W Receive Abort Detect Interrupt Enable
0: Receive abort detect interrupt is disabled
1: Receive abort detect interrupt is enabled
24
RFCOFIP 0
R/W Receive Frame Counter Overflow Interrupt Enable
0: Receive frame counter overflow interrupt is disabled
1: Receive frame counter overflow interrupt is enabled
23
ADEIP
0
R/W Address Error Interrupt Enable
0: Address error interrupt is disabled
1: Address error interrupt is enabled
22
ECIIP
0
R/W EtherC Status Register Source Interrupt Enable
0: EtherC status interrupt is disabled
1: EtherC status interrupt is enabled
21
TC0IP
0
R/W Frame Transmission Complete Interrupt Enable
0: Frame transmission complete interrupt is disabled
1: Frame transmission complete interrupt is enabled
20
TDEIP
0
R/W Transmit Descriptor Empty Interrupt Enable
0: Transmit descriptor empty interrupt is disabled
1: Transmit descriptor empty interrupt is enabled
19
TFUFIP
0
R/W Transmit FIFO Underflow Interrupt Enable
0: Underflow interrupt is disabled
1: Underflow interrupt is enabled
18
FRIP
0
R/W Frame Reception Interrupt Enable
0: Frame reception interrupt is disabled
1: Frame reception interrupt is enabled
17
RDEIP
0
R/W Receive Descriptor Empty Interrupt Enable
0: Receive descriptor empty interrupt is disabled
1: Receive descriptor empty interrupt is enabled
Rev. 1.00 Nov. 22, 2007 Page 764 of 1692
REJ09B0360-0100