SH7764 Datasheet, PDF (1305/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 24 Video Display Controller (VDC2)
24.6.9 α Control Registers (GROPEDPA2 to GROPEDPA4)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DEFA[7:0]
ACOEF[7:0]
Initial value: 1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
ARATE[7:0]
WE 
Initial value: 0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R
5
4
3
2
1
0
 AST 
AMOD[1:0] AEN
0
0
0
0
0
0
R R/W R R/W R/W R/W
Bit
31 to 24
23 to 16
Initial
Bit Name Value
DEFA[7:0] H'FF
ACOEF[7:0] H'00
15 to 8 ARATE[7:0] H'00
7
WE
0
6, 5

All 0
4
AST
0
3

0
R/W Description
R/W These bits specify the initial α value.
R/W These bits specify a coefficient for α value
calculation. This value is added to or subtracted
from the DEFA value.
R/W These bits specify the frame rate of α control.
(480p Vsync is used as the unit of counting.)
R/W Enables transfer of the α control register values.
Writing 1 to this bit transfers the register values
(registers at H'320 to H'328) in synchronization
with Vsync. After register transfer is competed, this
bit is cleared to 0.
0: Disables transfer
1: Enables transfer
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R
α blending status flag.
0: Addition or subtraction has been completed
1: Addition or subtraction is in progress
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 1.00 Nov. 22, 2007 Page 1249 of 1692
REJ09B0360-0100