SH7764 Datasheet, PDF (1126/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 G2D
For example, when the view point is Z = 0 as in the figure below, the parse transformation matrix
becomes (1). Therefore, the synthesized matrix obtained by combining the parse transformation
matrix with the affine transformation matrix becomes (2).
Screen
d
Ground
Z=0
1
0
0
0
Zmin
0
0
0
1
0
0
0
1
0
0
1/d
0
Zmax
(1)
m00
m01
0
m03
m10
m11
0
m13
(2)
0
0
0
0
m20/d
m21/d
0
m23/d
The above nine parameters are set to the matrix parameter A to I registers (MTRAR to MTRIR),
which are coordinate transformation control registers.
MTRAR to MTRIR are set in the single-precision floating-point format defined by the IEEE 754
standard. Since internal operation is executed in the 32-bit fixed-point mode (16-bit integer
portion and 16-bit fractional portion), parameters A to I should be set within the range of −2¹⁵ ≤
MTRAR to MTRIR < 2¹⁵. If a setting exceeds the above range when being transformed from a
single-precision floating-point value into a 32-bit fixed-point value, saturation processing is
executed. Note that parameters A to I must be set so that the matrix operation results TX, TY, and
Rev. 1.00 Nov. 22, 2007 Page 1070 of 1692
REJ09B0360-0100