SH7764 Datasheet, PDF (1242/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 G2D
Class
Area P4
Register Name Abbrev. RW WPR*1 Address*2
Area 7
Address*2
Access
Size
Coordinate
transformation
control
Matrix parameter MTRFR
F
Matrix parameter MTRGR
G
R/W Y
R/W Y
H'FFEA 0118 H'1FEA 0118 32
H'FFEA 011C H'1FEA 011C 32
Matrix parameter MTRHR R/W Y
H
H'FFEA 0120 H'1FEA 0120 32
Matrix parameter I MTRIR R/W Y
H'FFEA 0124 H'1FEA 0124 32
Coordinate
transformation
offset X
GTROFSX R/W Y
R
H'FFEA 0128 H'1FEA 0128 32
Coordinate
transformation
offset Y
GTROFSY R/W Y
R
H'FFEA 012C H'1FEA 012C 32
Z clipping area
MIN
ZCLPMIN R/W Y
R
H'FFEA 0130 H'1FEA 0130 32
Z clipping area
MAX
ZCLPMAX R/W Y
R
H'FFEA 0134 H'1FEA 0134 32
Z saturation value ZSATVMI R/W Y
MIN
NR
H'FFEA 0138 H'1FEA 0138 32
Notes: *1 Y: WPR command setting is enable. N: WPR command setting is not disable.
*2 The area P4 address is an address when accessing through area P4 in a virtual
address space. The area 7 address is an address when accessing through area 7 in a
physical space using the TLB.
Writing to the undefined address space is prohibited. If writing to such an address
space is done, the G2D operation is not guaranteed.
Rev. 1.00 Nov. 22, 2007 Page 1186 of 1692
REJ09B0360-0100