SH7764 Datasheet, PDF (743/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 18 Serial Sound Interface (SSI)
(g) Configuration Fields - Signal Format Fields
There are several more configuration bits in non-compressed mode which will now be
demonstrated. These bits are NOT mutually exclusive, however some bit combinations will
probably be prohibited.
They are demonstrated by referring to the following basic sample format shown in figure 18.9.
SWL = 6 bits (not attainable in SSI module, demonstration only)
DWL = 4 bits (not attainable in SSI module, demonstration only)
CHNL = 00, SCKP = 0, SWSP = 0, SPDP = 0, SDTA = 0, PDTA = 0, DEL = 0, MUEN = 0
4-bit data samples continuously written to SSITDR are transmitted onto the serial audio bus.
SSI_SCK
SSI_WS
1st channel
2nd channel
SSI_SDATA TD28 0 0 TD31 TD30 TD29 TD28 0 0 TD31 TD30 TD29 TD28 0 0 TD31
[Legend] (for this and following diagrams:)
Arrow head indicates sampling point of receiver
TDn
Bit n in SSITDR
0
means a low level on the serial bus (padding or mute)
1
means a high level on the serial bus (padding)
Figure 18.9 Basic Sample Format
(Transmit Mode with Example System/Data Word Length)
Rev. 1.00 Nov. 22, 2007 Page 687 of 1692
REJ09B0360-0100