SH7764 Datasheet, PDF (1371/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 25 NAND Flash Memory Controller (FLCTL)
25.4.5 ECC Error Correction
The FLCTL generates and adds an ECC code during write operation in sector access mode and
performs ECC error check during read operation in sector access mode. The FLCTL, however,
does not perform error correction. Note that errors must be corrected by software.
25.4.6 Status Read
The FLCTL can read the status register of a NAND-type flash memory. The data in the status
register of a NAND-type flash memory is input through the I/O7 to I/O0 pins and stored in the bits
STAT[7:0] in FLBSYCNT. The bits STAT[7:0] in FLBSYCNT can be read by the CPU. If a
program error or erase error is detected when the status register value is stored in the bits
STAT[7:0] in FLBSYCNT, the STERB bit in FLINTDMACR is set to 1 and generates an
interrupt to the CPU if the STERINTE bit in FLINTDMACR is enabled.
The status register of NAND-type flash memory can be read by inputting command H'70 to
NAND-type flash memory. If programming is executed in command access mode or sector access
mode while the DOSR bit in FLCMDCR is set to 1, the FLCTL automatically inputs command
H'70 to NAND-type flash memory and reads the status register of NAND-type flash memory.
When the status register of NAND-type flash memory is read, the I/O7 to I/O0 pins indicate the
following information as described in table 25.4.
Table 25.4 Status Read of NAND-Type Flash Memory
I/O
I/O7
I/O6
I/O5 to I/O1
I/O0
Status (definition)
Program protection
Ready/busy
Reserved
Program/erase
Description
0: Cannot be programmed
1: Can be programmed
0: Busy state
1: Ready state

0: Pass
1: Fail
Rev. 1.00 Nov. 22, 2007 Page 1315 of 1692
REJ09B0360-0100