SH7764 Datasheet, PDF (227/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 7 Memory Management Unit (MMU)
• SH: Share status bit
When 0, pages are not shared by processes.
When 1, pages are shared by processes.
• SZ[1:0]: Page size bits
Specify the page size.
00: 1-Kbyte page
01: 4-Kbyte page
10: 64-Kbyte page
11: 1-Mbyte page
• V: Validity bit
Indicates whether the entry is valid.
0: Invalid
1: Valid
Cleared to 0 by a power-on reset.
• PPN: Physical page number
Upper 22 bits of the physical address of the physical page number.
With a 1-Kbyte page, PPN[28:10] are valid.
With a 4-Kbyte page, PPN[28:12] are valid.
With a 64-Kbyte page, PPN[28:16] are valid.
With a 1-Mbyte page, PPN[28:20] are valid.
The synonym problem must be taken into account when setting the PPN (see section 7.5.5,
Avoiding Synonym Problems).
• PR[1:0]: Protection key data
2-bit data expressing the page access right as a code.
00: Can be read from only in privileged mode
01: Can be read from and written to in privileged mode
10: Can be read from only in privileged or user mode
11: Can be read from and written to in privileged mode or user mode
• C: Cacheability bit
Indicates whether a page is cacheable.
0: Not cacheable
1: Cacheable
When the control register area is mapped, this bit must be cleared to 0.
Rev. 1.00 Nov. 22, 2007 Page 171 of 1692
REJ09B0360-0100