SH7764 Datasheet, PDF (828/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 20 Ethernet Controller Direct Memory Access Controller (E-DMAC)
20.2.11 FIFO Depth Register (FDR)
FDR is a 32-bit readable/writable register that specifies the sizes of the transmit and receive
FIFOs.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
TFD[4:0]
—
—
—
RFD[4:0]
Initial value: 0
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
R/W: R R R R/W R/W R/W R/W R/W R R R R/W R/W R/W R/W R/W
Bit
Bit Name
31 to 13 
12 to 8 TFD[4:0]
7 to 5 
Initial
Value
All 0
B'00111
All 0
R/W
R
R/W
R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Transmit FIFO Size
Specifies the size of the transmit FIFO. The setting
must not be changed after transmission/reception has
started.
00000: 256 bytes
00001: 512 bytes
00010: 768 bytes
00011: 1024 bytes
00100: 1280 bytes
00101: 1536 bytes
00110: 1792 bytes
00111: 2048 bytes
Other than above: Setting prohibited
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Nov. 22, 2007 Page 772 of 1692
REJ09B0360-0100