SH7764 Datasheet, PDF (458/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 12 Direct Memory Access Controller (DMAC)
12.4.7 DREQ Pin Sampling Timing
Figures 12.13 to 12.16 show the sample timing of the DREQ input in each bus mode, respectively.
CLKOUT
Bus cycle
DREQ
(Rising edge)
CPU
1st acceptance
DMAC
CPU
2nd acceptance
DACK
(High-active)
: Non-sensitive period
Acceptance
started
Figure 12.13 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection
CLKOUT
Bus cycle
DREQ
(Overrun 0,
High-level)
DACK
(High-active)
CPU
1st acceptance
DMAC
CPU
2nd acceptance
Acceptance started
CLKOUT
Bus cycle
DREQ
(Overrun 1,
High-level)
CPU
1st acceptance
DMAC
CPU
2nd acceptance
DACK
(High-active)
: Non-sensitive period
Acceptance started
Figure 12.14 Example of DREQ Input Detection in Cycle Steal Mode Level Detection
Rev. 1.00 Nov. 22, 2007 Page 402 of 1692
REJ09B0360-0100