SH7764 Datasheet, PDF (653/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 17 ATAPI
17.3.4 PIO Timing Register (ATAPI_PIO_TIMING)
Set the machine cycle numbers to the following bits before the access to the ATAPI device.
The machine cycle is a pixel bus clock.
Bit: 31
—
Initial value: ₀
R/W: R
Bit: 15
—
Initial value: 0
R/W: R
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
—
pSDCT
pSDPW
pSDST
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
pMDCT
pMDPW
pMDST
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
31, 30
29 to 24
Bit Name
—
pSDCT
Initial
Value
All 0
0
23 to 19 pSDPW 0
18 to 16 pSDST
0
15, 14 —
All 0
13 to 8 pMDCT 0
7 to 3
pMDPW 0
2 to 0
pMDST 0
R/W Description
R
Reserved
R/W pSDCT sets the cycle time of the Slave ATAPI
device.
R/W pSDPW sets the IDEIORD/IDEIOWR pulse width
of the Slave ATAPI device.
R/W pSDST sets the address setup time to
IDEIORD/IDEIOWR for the slave ATAPI device in
the PIO mode.
R
Reserved
R/W pMDCT sets the cycle time of the Master ATAPI
device.
R/W pMDPW sets the IDEIORD/IDEIOWR pulse width
of the Master ATAPI device.
R/W pMDST sets the address setup time to
IDEIORD/IDEIOWR for the master ATAPI device in
the PIO mode.
Rev. 1.00 Nov. 22, 2007 Page 597 of 1692
REJ09B0360-0100