SH7764 Datasheet, PDF (1072/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 22 LCD Controller (LCDC)
22.3.6 LCDC Line Address Offset Register for Display Data Fetch (LDLAOR)
LDLAOR sets the address width of the Y-coordinates increment used for LCDC to read the image
recognized by the graphics driver. This register specifies how many bytes the address from which
data is to be read should be moved when the Y coordinates have been incremented by 1. This
register does not have to be equal to the horizontal width of the LCD panel. When the memory
address of a point (X, Y) in the two-dimensional image is calculated by Ax + By+ C, this register
becomes equal to B in this equation.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
LAO[15:0]
Initial value: 0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
15 to 0
Bit Name Initial Value R/W
LAO
H'0280
R/W
[15:0]
Description
Line Address Offset
The minimum alignment unit of LDLAOR is 32 bytes.
Because the LCDC handles these values as 32-byte
data, the values written to the lower five bits of the
register are always treated as 0. The lower five bits of
the register are always read as 0. The initial values (×
resolution = 640) will continuously and accurately
place the VGA (640 × 480 dots) display data without
skipping an address between lines.
A binary exponential at least as large as the horizontal
width of the image is recommended for the LDLAOR
value, taking into consideration the software operation
speed.
Rev. 1.00 Nov. 22, 2007 Page 1016 of 1692
REJ09B0360-0100