SH7764 Datasheet, PDF (1328/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 24 Video Display Controller (VDC2)
24.6.26 T1004 Control Register (T1004CNT)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
















Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
VSYNC HSYNC DEC












 _{_TYPE _TYPE _TYPE}
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R/W R/W R/W
Bit
31 to 3
Bit Name

Initial
Value
All 0
2
VSYNC_ 0
TYPE
1
HSYNC_ 0
TYPE
0
DEC_TYPE 0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Selects the polarity of VSYNC in T-1004 format.
0: Positive
1: Negative
R/W Selects the polarity of HSYNC in T-1004 format.
0: Positive
1: Negative
R/W Selects the polarity of DEC (data enable) in T-1004
format.
0: Positive
1: Negative
Rev. 1.00 Nov. 22, 2007 Page 1272 of 1692
REJ09B0360-0100