SH7764 Datasheet, PDF (42/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Figure 29.6 STATUS Output by Watchdog timer overflow Power-On Reset
during Normal Operation .........................................................................................1439
Figure 29.7 STATUS Output by Watchdog timer overflow Power-On Reset
during Sleep Mode ...................................................................................................1440
Section 30 User Break Controller (UBC)
Figure 30.1 Block Diagram of UBC............................................................................................1442
Figure 30.2 Flowchart of User Break Debugging Support Function ...........................................1469
Section 31 User Debugging Interface (H-UDI)
Figure 31.1 H-UDI Block Diagram .............................................................................................1478
Figure 31.2 Sequence for switching from Boundary-Scan TAP Controller to H-UDI................1481
Figure 31.3 TAP Controller State Transitions .............................................................................1506
Figure 31.4 H-UDI Reset.............................................................................................................1507
Section 33 Electrical Characteristics
Figure 33.1 Power-on/Power-off Sequence.................................................................................1574
Figure 33.2 EXTAL Clock Input Timing ....................................................................................1582
Figure 33.3 CLKOUT Clock Output Timing (1).........................................................................1583
Figure 33.4 Power-On Oscillation Settling Time ........................................................................1583
Figure 33.5 MODE Pin Setup / Hold Timing ..............................................................................1584
Figure 33.6 Pin Drive Timing in Standby....................................................................................1584
Figure 33.7 Control Signal Timing..............................................................................................1585
Figure 33.8 Basic Bus Cycle in SRAM Bus Cycle (No Wait Cycle) ..........................................1587
Figure 33.9 Basic Bus Cycle in SRAM Bus Cycle (One Internal Wait Cycle) ...........................1588
Figure 33.10 Basic Bus Cycle in SRAM Bus Cycle (Internal Wait Cycle +
One External Wait Cycle) ......................................................................................1589
Figure 33.11 Basic Bus Cycle in SRAM Bus Cycle (No Wait Cycle, Address Setup /
Hold Time Insert, AnS= 1, AnH= 1) ..................................................................... 1590
Figure 33.12 SRAM Bus Cycle in Bank Open Mode Read Bus Cycle (ACT-READ)
(BOMODE[1:0]= 00, SCL[2:0]= 000, SRCD= 0, CAS Latency= 2cyc,
IRCD= 2cyc)..........................................................................................................1591
Figure 33.13 SRAM Bus Cycle in Bank Open Mode Pre-charge Read Bus Cycle
(PRE-ACT-READ) (BOMODE[1:0]= 00, SRP[1:0]= 00, SCL[2:0]= 000,
SRCD=0, IRP= 2cyc, CAS Latency= 2cyc, IRCD= 2cyc) ...................................1592
Figure 33.14 SRAM Bus Cycle in Bank Open Mode Read Bus Cycle (Read)
(BOMODE[1:0]= 00, SCL[2:0]= 000, SRCD=0, CAS Latency= 2cyc,
IRCD= 2cyc)..........................................................................................................1593
Figure 33.15 SRAM Bus Cycle in Bank Open Mode Write Bus Cycle (ACT-WRITE)
(BOMODE[1:0]= 00, SRCD= 0, IRCD= 2cyc).....................................................1594
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