SH7764 Datasheet, PDF (651/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 17 ATAPI
Initial
Bit
Bit Name Value R/W Description
4
DEVINT 0
R
DEVINT is ATAPI device interrupt IDEINT status. This
bit is read only. Since this bit does not hold its status in
this module, if IDEINT becomes 0, this bit will also
become 0. ATAPI interface treats the interrupt signal
from the ATAPI device as a level-triggered input.
According to the ATAPI standard, IDEINT will be
negated by the ATAPI device within 400 ns of the
negation of IDEIORD that reads the Status register to
clear a pending interrupt.
3
TOUT 0
R/WC0
TOUT indicates that an IORDY timeout is detected.
Timeout is detected if no response is returned (the
IDEIORDY pin is at the Low level.) in 150 cycles or
longer of Pixel Bus clock cycle time. Writing 0 resets this
register.
2
ERR
0
R/WC0 ERR is set to 1 when a DMA abort is detected. ERR=1
occurs if:
1. The host brings DMA transfer to a forced stop.
2. DTCD=1 and ACT=0 because of device termination
Writing 0 resets this register.
1
NEND 0
R/WC0 NEND is a DMA normal end. Writing 0 resets this
register.
0
ACT
0
R
ACT indicates that the DMA is active. This bit is read
only. This register is cleared when the DMA transfer is
completed.
This bit should not be used as an interrupt source.
Rev. 1.00 Nov. 22, 2007 Page 595 of 1692
REJ09B0360-0100