SH7764 Datasheet, PDF (65/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 1 Overview
Items
Specification
Ethernet controller
(EtherC)
• Ethernet MAC (Media Access Control) function
Data frame assembly/disassembly (frame format conforming to
IEEE802.3)
CSMA/CD link management (data collision prevention and collision
processing)
CRC processing
Separate 2-Kbyte FIFOs for transmission and reception
Full-duplex or half-duplex transmission and reception
Detects short packets and long packets
• Conforms to MII (Media Independent Interface) standard
Station management (STA function)
10 or 100-Mbps transfer rate
• Magic Packet detection (WOL (Wake-On-LAN) signal output)
DMAC for Ethernet • Reduces the load on the CPU by means of a descriptor management
controller (E-DMAC)
system
• One channel for data transfer from the Ether receive FIFO (2 Kbytes)
to receive buffer
• One channel for data transfer from the transmit buffer to EtherC
transmit FIFO (2 Kbytes)
• Achieves efficient bus utilization through 32-byte burst transfer
• Supports single-frame multi-buffer transfer
USB host/function
interface (USB)
• Conforms to USB version 2.0
• Supports 480-Mbps and 12-Mbps transfer speeds
• Can be switched between the USB host and function by software
• PHY is provided
• Connectable with multiple peripheral devices through a hub
• 5-Kbyte RAM provided as a communication buffer
LCD controller (LCDC) • Supports 16 x 1 to 1024 x 1024-dot display size
• Supports 4, 8, 15, and 16 bpp color modes
• Supports 1, 2, 4, and 6 bpp grayscale modes
• Supports TFT, DSTN, and STN display
• Selectable signal polarities
• 24-bit color palette memory (16 of 24 bits are valid: R: 5; G: 6; B: 5)
• Unified graphics memory architecture
Rev. 1.00 Nov. 22, 2007 Page 9 of 1692
REJ09B0360-0100