SH7764 Datasheet, PDF (325/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Initial
Bit
Bit Name Value R/W
27 to 16 DRI11 to H'61A R/W
DRI0
15 to 10 
All 0 R
9
DRE
0
R/W
Section 11 Memory Controller Unit (MCU)
Description
DRAM Refresh Interval
When refreshing is valid (DRE = 1), the maximum
refresh interval (for auto-refreshing) can be specified by
these bits. One count is the same as the cycle of the
memory clock.
At 100-MHz operation, one count corresponds to 10 ns.
The minimum settable value is H'020. If a set value is
less than H'020, H'020 is added to the count value.
The MCU has a 12-bit internal counter. When the DCE
or DRE bit is 0, or the RMODE bit is 1, this counter is
cleared to 0. Otherwise, this counter increments on
each external clock pulse. The counter value is
compared with the DRI bits, and if a match occurs, an
auto-refresh request is generated in the MCU and auto-
refreshing is performed. Note that the counter is
cleared to 0 at a match, and then begins incrementing
again. The maximum of one internally generated auto-
refresh request is recorded, and if bits DCE, DRE, and
RMODE are 110, respectively, an auto-refresh request
is never cleared until auto-refreshing is performed. The
DRE bit should be cleared to 0 before writing to the DRI
bits, and set to 1 after the writing has completed. In this
case, the previous written value should be set to the
DRI bits.
Note: While the bus is released, a refresh request is
generated when the counter increments up to
one-half of the set value.
Reserved
These bits are always read as 0. The write value should
always be 0.
DRAM Refresh Enable
This bit sets whether refresh mode is valid or invalid.
1: Valid
0: Invalid
Rev. 1.00 Nov. 22, 2007 Page 269 of 1692
REJ09B0360-0100