SH7764 Datasheet, PDF (1352/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 25 NAND Flash Memory Controller (FLCTL)
Initial
Bit
Bit Name Value R/W Description
15 to 8 DT[15:8] H'00
R/W Second Data
Specify the 2nd data to be input or output via the FD7
to FD0 pins.
In write: Specify write data
In read: Store read data
7 to 0 DT[7:0] H'00
R/W First Data
Specify the 1st data to be input or output via the FD7 to
FD0 pins.
In write: Specify write data
In read: Store read data
25.3.8 Interrupt DMA Control Register (FLINTDMACR)
FLINTDMACR is a 32-bit readable/writable register that enables or disables DMA transfer
requests or interrupts. A transfer request from the FLCTL to the DMAC is issued after each access
mode has been started.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
—
—
—
—
—
—
—
ECER
INTE
—
—
FIFOTRG
[1:0]
AC1 AC0 DREQ1 DREQ0
CLR CLR EN EN
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R/W R R R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
EC ST BTO TRR TRR STER RBER TE TR TR
ERB ERB ERB EQF1 EQF0 INTE INTE INTE INTE1 INTE0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
31 to 25 —
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
24
ECERINTE 0
R/W ECC Error Interrupt Enable
0: Disables an interrupt when an ECC error occurs
1: Enables an interrupt when an ECC error occurs
Rev. 1.00 Nov. 22, 2007 Page 1296 of 1692
REJ09B0360-0100