SH7764 Datasheet, PDF (944/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 21 USB 2.0 Host/Function Module (USB)
Bit
Bit Name
2
CCPL
Initial
Value
0
R/W
R/W*¹
Description
Control Transfer End Enable
When the function controller function is selected,
setting this bit to 1 enables the status stage of the
control transfer to be completed.
0: Invalid
1: Completion of control transfer is enabled.
When software sets this bit to 1 while the
corresponding PID bits are set to BUF, this module
completes the control transfer stage.
Specifically, during control read transfer, this
module transmits the ACK handshake in response
to the OUT transaction from the USB host, and
outputs the zero-length packet in response to the IN
transaction from the USB host during control write
or no-data control transfer. However, on detecting
the SET_ADDRESS request, this module operates
in auto response mode from the setup stage up to
the status stage completion irrespective of the
setting of this bit.
This module modifies this bit from 1 to 0 on
receiving the new setup packet.
Software cannot write 1 to this bit while VALID is 1.
When the host controller function is selected, be
sure to write 0 to this bit.
Rev. 1.00 Nov. 22, 2007 Page 888 of 1692
REJ09B0360-0100