SH7764 Datasheet, PDF (62/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 1 Overview
Items
Memory control unit
(MCU)
Specification
• Supports external memory access
 Outputs four external memory select signals
 Supports four external memory areas (FLASH, SDRAM), each of
which has 64 Mbytes max.
• SRAM: 32-, 16-, or 8-bit data bus width selectable
• SDRAM: 64- or 32-bit data bus width selectable
• Big endian or little endian mode can be set
[SRAM interface]
• NOR-type flash memory can be connected
• Cycle wait function: Wait control by hardware through signals
• Wait control for preventing collisions on the data bus (idle cycle
insertion):
 Wait setting between read cycles
 Wait setting between a read cycle and a write cycle
[SDRAM interface]
• Refresh function:
 Auto-refresh (programmable refresh counter provided)
 Self-refresh
• Timing control:
Row-column latency, column latency, row active period, write recovery
period, row precharge period, auto-refresh request interval, initial
precharge cycle count, and initial auto-refresh request interval
• Burst access mode: Random column (SDRAM burst length: eight for
32-bit bus or four for 64-bit bus)
• Initialization sequencer function: Issues precharge and auto-refresh
commands
Rev. 1.00 Nov. 22, 2007 Page 6 of 1692
REJ09B0360-0100