SH7764 Datasheet, PDF (1119/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

22.6 Usage Notes
Section 22 LCD Controller (LCDC)
22.6.1 Procedure for Halting Access to Display Data Storage VRAM (SDRAM in Area 1
or 2)
Follow the procedure below to halt access to VRAM for storing display data (SDRAM in area 1 or
2).
Procedure for Halting Access to Display Data Storage VRAM:
1. Confirm that the LPS1 and LPS0 bits in LDPMMR are currently set to 1.
2. Clear the DON bit in LDCNTR to 0 (display-off mode).
3. Confirm that the LPS1 and LPS0 bits in LDPMMR have changed to 0.
4. Wait for the display time for a single frame to elapse.
This halting procedure is required before selecting self-refreshing for the display data storage
VRAM (SDRAM in area 1 or 2) or making a transition to standby mode or module standby mode.
22.6.2 Notes on Holding the Access Request by MCU
If the NMIFL bit in the NMIFCR register is set to 1 by an NMI interrupt when both the NMIME
(bit 24) bit and the LCDM (bit 16) bit are 1 in the request mask setting register (RQM) of MCU,
the LCDC cannot access the VRAM that is used for the display data storage (SDRAM in area 1 or
2). The access request is held, if the LCDC attempts access the VRAM.
As the LCDC continues to output data stored in the line buffer to the LCD panel data pin, the LCD
display will be stopped if the line buffer becomes empty. Accordingly, NMI interrupts should be
disabled and the NMIFL bit should be cleared to 0 before the line buffer becomes empty.
If a bus release request is accepted from the an external device, the LCDC also cannot access the
VRAM and the access request is held. Acquire the bus mastership again before the line buffer
becomes empty as in the case of the NMI interrupt.
Rev. 1.00 Nov. 22, 2007 Page 1063 of 1692
REJ09B0360-0100