SH7764 Datasheet, PDF (49/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Table 11.11
Table 11.12
Table 11.13
Table 11.14
Table 11.15
Table 11.16
Table 11.17
Table 11.18
Table 11.19
16-Bit External Device/Little-Endian Access and Data Alignment
(Areas 0 and 3).................................................................................................. 310
8-Bit External Device/Little-Endian Access and Data Alignment
(Areas 0 and 3).................................................................................................. 311
32-Bit External Device/Big-Endian Access and Data Alignment
(Areas 1 and 2).................................................................................................. 312
32-Bit External Device/Little-Endian Access and Data Alignment
(Areas 1 and 2).................................................................................................. 313
64-Bit External Device/Big-Endian Access and Data Alignment
(Areas 1 and 2).................................................................................................. 314
64-Bit External Device/Little-Endian Access and Data Alignment
(Areas 1 and 2).................................................................................................. 315
Supported Commands for SDRAM .................................................................. 324
SDRAM Bus Widths and Address Multiplexing
(External Bus Width is 32 Bits) ........................................................................ 327
Correspondence between Linear Addresses and Tiled Memory Addresses...... 355
Section 12 Direct Memory Access Controller (DMAC)
Table 12.1 Pin Configuration.................................................................................................. 361
Table 12.2 Register Configuration of DMAC......................................................................... 362
Table 12.3 State of Registers in Each Operating Mode .......................................................... 364
Table 12.4 Transfer Request Sources ..................................................................................... 383
Table 12.5 Setting External Request Mode with RS Bits ....................................................... 384
Table 12.6 Selecting External Request Detection with DL, DS Bits ...................................... 385
Table 12.7 Selecting External Request Detection with DO Bit .............................................. 385
Table 12.8 Selecting On-Chip Peripheral Module Request Modes with Bits RS[3:0] ........... 386
Table 12.9 DMA Transfer Matrix in Auto-Request Mode ..................................................... 396
Table 12.10 DMA Transfer Matrix in External Request Mode (Only Channels 0 and 1) .... 396
Table 12.11 DMA Transfer Matrix in On-Chip Peripheral module Request Mode.............. 397
Section 13 Interrupt Controller (INTC)
Table 13.1 Interrupt Types...................................................................................................... 412
Table 13.2 INTC Pin Configuration ....................................................................................... 414
Table 13.3 INTC Register Configuration ............................................................................... 415
Table 13.4 Register States in Each Operating Mode .............................................................. 417
Table 13.5 Interrupt Request Sources and INT2PRI0 to INT2PRI12..................................... 431
Table 13.6 Interrupt Exception Handling and Priority............................................................ 458
Table 13.7 Interrupt Response Time....................................................................................... 465
Table 13.8 Switching Sequence of IRQ1 and IRQ0 Pin Function.......................................... 467
Rev. 1.00 Nov. 22, 2007 Page xlix of lvi