SH7764 Datasheet, PDF (643/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 17 ATAPI
Section 17 ATAPI
The ATAPI interface provides both the ATA and ATAPI physical interfaces. This device also
supports both the ATA task and ATAPI packet commands.
17.1 Features
• Supporting primary channel
• Supporting master/slave
• Supporting 3.3V I/O interface
• Supporting PIO modes 0 to 4, the multiword DMA modes 0 to 2, and the Ultra DMA modes 0
to 4
• Supporting descriptor mode
Figure 17.1 shows a block diagram of the ATAPI.
I/O bus
Pixel bus
I/O bus
interface
For PIO transfer
Physical
interface
ATAPI
interface
control
register
Pixel bus
interface
DMA control
FIFO
(32 bytes)
Double buffer
For DMA
transfer
CRC
Figure 17.1 ATAPI Block Diagram
IDED[15:0]
IDEA[2:0]
IODACK
IODREQ
IDECS[1:0]
IDEIOWR
IDEIORD
IDEIORDY
IDEINT
IDERST
DIRECTION
Rev. 1.00 Nov. 22, 2007 Page 587 of 1692
REJ09B0360-0100