SH7764 Datasheet, PDF (617/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 16 I²C Bus Interface
Bit
Bit Name Initial Value R/W Description
1
SDR
0
R/W* Slave Data Received
A byte of data has been received from the bus
and is ready for read in the receive data
register. This bit becomes active after the
falling edge of SCL during the last data bit.
During the single-buffer mode, this bit must be
reset after data has been read from the ICRXD
register.
When SDBS is set to 1, SCL will be held low
from the timing when the receive data register
acquires the data packet until the SDR flag is
cleared.
0
SAR
0
R/W* Slave Address Received
Indicates that the slave has recognized its own
address on the bus (defined by the contents of
the slave address register). If the general call
acknowledgement enable bit is enabled in the
slave control register, then this status bit is
also set to 1 even if the address on the bus is
a general call address. In this case, the GCAR
bit in this register is used to determine whether
or not the address is a general call address.
The STM bit indicates whether the access is
read (high) or write (low). This status becomes
active after the falling edge of SCL during the
last address bit. The slave holds SCL low
during the start of the ACK phase until the
software resets this status bit.
Note: * This bit can be read from or written to. Writing 0 clears this bit to 0 and writing 1 is
ignored.
Rev. 1.00 Nov. 22, 2007 Page 561 of 1692
REJ09B0360-0100