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SH7764 Datasheet, PDF (164/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series | |||
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Section 5 Exception Handling
5.6 Description of Exceptions
The various exception handling operations explained here are exception sources, transition address
on the occurrence of exception, and processor operation when a transition is made.
5.6.1 Resets
(1) Power-On Reset
⢠Condition:
Power-on reset request
⢠Operations:
Exception code H'000 is set in EXPEVT, initialization of the CPU and on-chip peripheral
module is carried out, and then a branch is made to the reset vector (H'A0000000). For details,
see the register descriptions in the relevant sections. A power-on reset should be executed
when power is supplied.
(2) H-UDI Reset
⢠Source: SDIR.TI[7:4] = B'0110 (negation) or B'0111 (assertion)
⢠Transition address: H'A0000000
⢠Transition operations:
Exception code H'000 is set in EXPEVT, initialization of VBR and SR is performed, and a
branch is made to PC = H'A0000000.
CPU and on-chip peripheral module initialization is performed. For details, see the register
descriptions in the relevant sections.
Rev. 1.00 Nov. 22, 2007 Page 108 of 1692
REJ09B0360-0100
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