SH7764 Datasheet, PDF (121/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 3 Instruction Set
Table 3.8 Branch Instructions
Instruction
BF
label
BF/S
label
BT
label
BT/S
label
BRA
BRAF
BSR
BSRF
JMP
JSR
RTS
label
Rn
label
Rn
@Rn
@Rn
Operation
Instruction Code
Privileged T Bit
When T = 0, disp × 2 + PC + 10001011dddddddd —
—
4 → PC
When T = 1, nop
Delayed branch; when T = 0, 10001111dddddddd —
—
disp × 2 + PC + 4 → PC
When T = 1, nop
When T = 1, disp × 2 + PC + 10001001dddddddd —
—
4 → PC
When T = 0, nop
Delayed branch; when T = 1, 10001101dddddddd —
—
disp × 2 + PC + 4 → PC
When T = 0, nop
Delayed branch, disp × 2 +
1010dddddddddddd —
—
PC + 4 → PC
Delayed branch, Rn + PC + 4 → 0000nnnn00100011 —
—
PC
Delayed branch, PC + 4 → PR, 1011dddddddddddd —
—
disp × 2 + PC + 4 → PC
Delayed branch, PC + 4 → PR, 0000nnnn00000011 —
—
Rn + PC + 4 → PC
Delayed branch, Rn → PC
0100nnnn00101011 —
—
Delayed branch, PC + 4 → PR, 0100nnnn00001011 —
—
Rn → PC
Delayed branch, PR → PC
0000000000001011 —
—
New
—
—
—
—
—
—
—
—
—
—
—
Table 3.9 System Control Instructions
Instruction
CLRMAC
CLRS
CLRT
ICBI
@Rn
LDC
Rm,SR
LDC
Rm,GBR
LDC
Rm,VBR
LDC
Rm,SGR
Operation
Instruction Code
Privileged T Bit
0 → MACH, MACL
0000000000101000 —
—
0→S
0000000001001000 —
—
0→T
0000000000001000 —
0
Invalidates instruction cache block 0000nnnn11100011 

Rm → SR
0100mmmm00001110 Privileged LSB
Rm → GBR
0100mmmm00011110 —
—
Rm → VBR
0100mmmm00101110 Privileged —
Rm → SGR
0100mmmm00111010 Privileged —
New
—
—
—
New
—
—
—
—
Rev. 1.00 Nov. 22, 2007 Page 65 of 1692
REJ09B0360-0100