SH7764 Datasheet, PDF (1061/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 22 LCD Controller (LCDC)
Register Name
Area P4
Abbreviation R/W Address*
Area 7
Address*
Access
Size
LCDC control register
LDCNTR R/W H'FFE3 0428 H'1FE3 0428 16
LCDC user specified interrupt
control register
LDUINTR R/W H'FFE3 0434 H'1FE3 0434 16
LCDC user specified interrupt line LDUINTLNR R/W H'FFE3 0436 H'1FE3 0436 16
number register
LCDC memory access interval
number register
LDLIRNR R/W H'FFE3 0440 H'1FE3 0440 16
Note: * P4 addresses are used when area P4 in the virtual address space is used, and area 7
addresses are used when accessing the register through area 7 in the physical address
space using the TLB.
Table 22.3 Register State in Each Operating Mode
Register Name
Abbreviation
Palette data register 00 to FF
LDPR00 to
LDPRFF
LCDC input clock register
LDICKR
LCDC module type register
LDMTR
LCDC data format register
LDDFR
LCDC data fetch start address
register for upper display panel
LDSARU
LCDC data fetch start address
register for lower display panel
LDSARL
LCDC fetch data line address offset LDLAOR
register for display panel
LCDC palette control register
LDPALCR
LCDC horizontal character number LDHCNR
register
LCDC horizontal synchronization LDHSYNR
signal register
LCDC vertical displayed line
number register
LDVDLNR
LCDC vertical total line number
register
LDVTLNR
Power-On
Reset
Undefined
H'1101
H'0109
H'000C
H'04000000
H'04000000
H'0280
H'0000
H'4F52
H'0050
H'01DF
H'01DF
Sleep
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Standby
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Rev. 1.00 Nov. 22, 2007 Page 1005 of 1692
REJ09B0360-0100