SH7764 Datasheet, PDF (1324/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 24 Video Display Controller (VDC2)
CLS
SPS (low-active)
Last line
First line
Second line
COM
Frame (internal signal)
Frame timing (when COMTIM_V = 0)
Figure 24.13 COM Signal Timing
24.6.23 SGDE Area Start Position Register (SGDESTART)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16






SGDE_START_V[9:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0





SGDE_START_H[10:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name
Value R/W Description
31 to 26 
All 0 R
Reserved
These bits are always read as 0. The write value
should always be 0.
25 to 16 SGDE_START H'000 R/W
_V[9:0]
These bits specify in number of lines the vertical
interval between the internal vertical sync signal
and the start of the data enable (DE) signal output.
Setting to 0 is prohibited.
15 to 11 
All 0 R
Reserved
These bits are always read as 0. The write value
should always be 0.
10 to 0 SGDE_START H'000 R/W
_H[10:0]
These bits specify in number of panel clock cycles
the horizontal interval between the internal
horizontal sync signal and the start of the data
enable (DE) signal output.
Notes: 1. Be sure to satisfy SYN_HEIGHT > SGDE_HEIGHT + SGDE_START_V; otherwise,
correct operation is not guaranteed.
2. Be sure to satisfy SYN_WIDTH > SGDE_WIDTH + SGDE_START_H; otherwise,
correct operation is not guaranteed.
Rev. 1.00 Nov. 22, 2007 Page 1268 of 1692
REJ09B0360-0100