SH7764 Datasheet, PDF (326/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Memory Controller Unit (MCU)
Initial
Bit
Bit Name Value R/W
Description
8
ENDIAN *
R
This bit indicates whether the external data bus is
operating in big endian mode or little endian mode.
1: Big endian mode
0: Little endian mode
Writing to this bit is invalid.
7, 6
BW1 and 01
BW0
R/W
Bus Width
These bits specify the SDRAM bus width. The width is
either 32 bits or 64 bits according to the setting of these
bits.
00: Setting prohibited
01: 32 bits wide
10: 64 bits wide
11: Setting prohibited
5 to 1 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
0
DCE
0
R/W
DRAM Controller Enable
This bit enables the SDRAM control by the MCU. When
this bit is 1, the SDRAM control by the MCU is enabled.
When this bit is 0, the MCU returns an error response
to the request sent via the SuperHyway bus.
Accordingly, the DCE bit should always be set to 1
while the SDRAM is operating.
Note: * Setting of the registers used for SDRAM control is applied to both area 1 and area 2.
Individual setting for each area cannot be made.
Rev. 1.00 Nov. 22, 2007 Page 270 of 1692
REJ09B0360-0100