SH7764 Datasheet, PDF (655/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Bit
Bit Name Initial
Value
15 to 11 —
All 0
10 to 5 mMDCT 0
4 to 0 mMDPW 0
Section 17 ATAPI
R/W Description
R
Reserved
R/W mMDCT sets the cycle time of the Master ATAPI
device.
R/W mMDPW sets the IDEIORD/IDEIOWR pulse width of
the Master ATAPI device.
IDEIORD/
IDEIOWR
DCT
DPW
DCT: Cycle setting
DPW: Setting the low pulse width for IDEIORD/IDEIOWR
Note: The prefix nS means slave and the prefix mM means master. DCT and DPW are set by multiplying the setting of
each register by the cycle of the Pixcelclk.
Figure 17.3 Multiword DMA Timing Register
Multiword DMA timing register value table
Pixel Bus Clock
100 MHz
Mode 0
H'0637
Mode 1
H'0209
Mode 2
H'01A8
Rev. 1.00 Nov. 22, 2007 Page 599 of 1692
REJ09B0360-0100