SH7764 Datasheet, PDF (1468/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 28 Power-Down Mode
Table 28.1 lists the states of the CPU and on-chip peripheral modules in each mode.
Table 28.1 States in Power-Down Modes
State
Power-
Down
Mode
Transition
Condition
CPG
CPU
On-Chip
Memory
On-Chip
Peripheral
Module
Pin
DDR-
SDRAM
Cancellation
S1*² S0*²
Sleep
SLEEP
Run
instruction
executed with
STBY = 0 in
STBCR
Halt
Retained Run
(register
contents
retained)
Held
AR or SR*¹ - Interrupt
- Power-on
reset
10
Refresh SLEEP
Halt
standby instruction
executed with
STBY = 1 in
STBCR
Halt
Halt
Halt
(register
(contents
contents retained)
retained)
Held (only
CLKOUT
operates)
SR*¹
- NMI or IRQ
- Power-on
reset
01
Module
Corresponding Run
Run
Run
Selected Held
AR or SR*¹ Clear
00
standby bit in MSTPCR0/
modules halt
corresponding bit
MSTPCR1 set to
in MSTPCR0/
1
MSTPCR1 to 0
Power-on PRESET pin
reset
driven low
Initial state Initial state Initial state Initial state Initial state Initial state 
11
Normal
operation
Run
Run
Run
Run
Run
Run

00
Notes: 1. AF: auto-refresh: SF: self-refresh
2. S1 and S0 are the output states on the STATUS1 and STATUS0 pins, respectively.
Rev. 1.00 Nov. 22, 2007 Page 1412 of 1692
REJ09B0360-0100