SH7764 Datasheet, PDF (1001/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 21 USB 2.0 Host/Function Module (USB)
(1) Zero-length packet reception or data packet reception when BFRE = 0
(short packet reception/transaction counter completion/buffer full)
USB bus
Token packet
Zero-length packet/
short data packet/
data packet (full)
(transaction count)
ACK handshake
BRDY
interrupt
A BRDY interrupt is generated
because reading from the buffer
is enabled.
(2) Data packet reception when BFRE = 1 (short packet reception/transaction counter completion)
USB bus
Token packet
Short data packet/
data packet
(transaction count)
ACK handshake
Buffer read
BRDY
interrupt
(3) Packet transmission
USB bus
Buffer write
A BRDY interrupt is generated
because the transfer has ended.
Token packet
Data packet
ACK handshake
BRDY
interrupt
A BRDY interrupt is generated
because writing to the buffer is enabled.
Figure 21.3 Timing at which a BRDY Interrupt is Generated
Rev. 1.00 Nov. 22, 2007 Page 945 of 1692
REJ09B0360-0100