SH7764 Datasheet, PDF (217/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 7 Memory Management Unit (MMU)
Initial
Bit
Bit Name Value R/W Description
8
V
Undefined R/W Page Management Information
7
SZ1
Undefined R/W The meaning of each bit is same as that of
6
PR1
Undefined R/W ^{corresponding bit in Common TLB (UTLB).}
5
PR0
Undefined R/W
For details, see section 7.3, TLB Functions (TLB
Compatible Mode; MMUCR.ME = 0) and section 7.4,
4
SZ0
Undefined R/W _{TLB Functions (TLB Extended Mode; MMUCR.ME = 1).}
3
C
2
D
Undefined R/W Note: SZ1, PR1, SZ0, and PR0 bits are valid only in
Undefined R/W
TLB compatible mode.
1
SH
Undefined R/W
0
WT
Undefined R/W
7.2.3 Translation Table Base Register (TTB)
TTB is used to store the base address of the currently used page table, and so on. The contents of
TTB are not changed unless a software directive is issued. This register can be used freely by
software.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TTB
Initial value:
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TTB
Initial value:
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 1.00 Nov. 22, 2007 Page 161 of 1692
REJ09B0360-0100