SH7764 Datasheet, PDF (1360/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 25 NAND Flash Memory Controller (FLCTL)
Bit
7 to 0
Bit Name
Initial
Value R/W Description
DTFO[7:0] H'00 R/W Fourth Data
Specify 4th data to be input or output via the FD7 to
FD0 pins.
In write: Specify write data
In read: Store read data
25.3.12 Control Code FIFO Register (FLECFIFO)
FLECFIFO is used to read or write the control code FIFO area.
In DMA transfer, data in this register must be specified as the destination (source).
Note that the direction of read or write specified by the SELRW bit in FLCMDCR must match
that specified in this register.
When transferring 16-byte DMA, access FLECFIFO from the address on the 16-byte address
boundary.
Before accessing the FLECFIFO, clear the FIFO data by setting the AC1CLR bit in the
FINTDMACR to 1.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECFO[31:24]
ECFO[23:16]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
ECFO[15:8]
ECFO[7:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
31 to 24 ECFO
[31:24]
Initial
Value R/W
H'00 R/W
Description
First Data
Specify 1st data to be input or output via the FD7 to
FD0 pins.
In write: Specify write data
In read: Store read data
Rev. 1.00 Nov. 22, 2007 Page 1304 of 1692
REJ09B0360-0100