SH7764 Datasheet, PDF (351/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Memory Controller Unit (MCU)
Initial
Bit
Bit Name Value R/W
7
RDSPL 1
R/W
6 to 0 
All 0
R
Description
RD Hold Cycle
This bit specifies the number of cycles to be inserted
into the RD assertion period to ensure the data hold
time to the read data sample timing. When this bit is set
to 1, the number of delay cycles between the RD
negation and the CS0 negation should be set to 1 or
more by setting the RDH bits in CS0WCR.
Note that, by setting this bit to 1, the number of delay
cycles between the RD negation and the CS0 negation
is reduced by 1.
0: No hold cycles inserted
1: 1 hold cycle inserted
Reserved
These bits are always read as 0. The write value
should always be 0.
11.4.14 CSn Wait Control Register (CSnWCR)
Bit: 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48

Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ADS[2:0]

ADH[2:0]

RDS[2:0]

RDH[2:0]
Initial value: 0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
R/W: R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0

WTS[2:0]

WTH[2:0]

BSH[2:0]
IW[3:0]
Initial value: 0
1
1
1
0
1
1
1
0
0
0
0
1
1
1
1
R/W: R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W
Rev. 1.00 Nov. 22, 2007 Page 295 of 1692
REJ09B0360-0100