SH7764 Datasheet, PDF (352/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Memory Controller Unit (MCU)
Initial
Bit
Bit Name Value R/W
63 to 31 
All 0 R
30 to 28 ADS2 to 111 R/W
ADS0
27

0
R
26 to 24 ADH2 to 111 R/W
ADH0
23

0
R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Address Setup Cycles
These bits specify the number of cycles to be inserted
to ensure the address setup time to the CSn assertion.
000: No cycles inserted
001: 1 cycle inserted
010: 2 cycles inserted
011: 3 cycles inserted
100: 4 cycles inserted
101: 5 cycles inserted
110: 6 cycles inserted
111: 7 cycles inserted
Reserved
This bit is always read as 0. The write value should
always be 0.
Address Hold Cycles
These bits specify the number of cycles to be inserted
to ensure the address hold time to the CSn negation.
000: No cycles inserted
001: 1 cycle inserted
010: 2 cycles inserted
011: 3 cycles inserted
100: 4 cycles inserted
101: 5 cycles inserted
110: 6 cycles inserted
111: 7 cycles inserted
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 1.00 Nov. 22, 2007 Page 296 of 1692
REJ09B0360-0100