SH7764 Datasheet, PDF (1081/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 22 LCD Controller (LCDC)
22.3.15 LCDC Interrupt Control Register (LDINTR)
LDINTR specifies where to control the Vsync interrupt of the LCD module. See also section
22.3.19, LCDC User Specified Interrupt Control Register (LDUINTR) and section 22.3.20, LCDC
User Specified Interrupt Line Number Register (LDUINTLNR) for interrupts. Note that
operations by this register setting and LCDC user specified interrupt control register (LDUINTR)
setting are independent.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
MINT
EN
FINT
EN
VSINT
EN
VEINT
EN
MINTS
FINTS VSINTS VEINTS








Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R
R
R
R
R
R
R
R
Bit
Bit Name Initial Value R/W Description
15
MINTEN 0
R/W Memory Access Interrupt Enable
Enables or disables an interrupt generation at the
start point of each vertical retrace line period for
VRAM access by LCDC.
0: Disables an interrupt generation at the start point
of each vertical retrace line period for VRAM
access
1: Enables an interrupt generation at the start point
of each vertical retrace line period for VRAM
access
14
FINTEN 0
R/W Frame End Interrupt Enable
Enables or disables the generation of an interrupt
after the last pixel of a frame is output to LDC panel.
0: Disables an interrupt generation when the last
pixel of the frame is output
1: Enables an interrupt generation when the last
pixel of the frame is output
13
VSINTEN 0
R/W Vsync Starting Point Interrupt Enable
Enables or disables the generation of an interrupt at
the start point of LCDC's Vsync.
0: Interrupt at the start point of the Vsync is disabled
1: Interrupt at the start point of the Vsync is enabled
Rev. 1.00 Nov. 22, 2007 Page 1025 of 1692
REJ09B0360-0100