SH7764 Datasheet, PDF (1322/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 24 Video Display Controller (VDC2)
24.6.21 Sampling Start Signal Timing Control Register (SPLTIM)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16





SPL_START[10:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0





SPL_END[10:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
31 to 27 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
26 to 16 SPL_START H'000 R/W These bits specify in number of panel clock cycles
[10:0]
the interval between the internal horizontal sync
signal and the point where the sampling start
signal (SPL) is set to 1.
15 to 11 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
10 to 0 SPL_END H'000 R/W These bits specify in number of panel clock cycles
[10:0]
the interval between the internal horizontal sync
signal and the point where the sampling start
signal (SPL) is cleared to 0.
Note: Be sure to satisfy SPL_START ≠ SPL_END; otherwise, correct operation is not guaranteed.
Rev. 1.00 Nov. 22, 2007 Page 1266 of 1692
REJ09B0360-0100